Teaching
Below are the modules I currently teach at TCD.
Michaelmas Term (Sept--Dec)
EEU2E6: Electronics
Offered to the 2nd year Engineering cohort, this module delves into dynamic circuit elements, transient and steady-state analysis of linear circuits with passive circuit elements and subsequently introducing active circuit components (diodes, linear amplifers) and steady-state analysis of diode circuits, linear amplifiers and operational amplifers for analogue computing. The module descriptor can be found here . The module is jointly taught with Prof. J. King.
EEU4C1/EE5M1: Integrated Systems Design
This module expands on the introductory digital design module in year 3 investigating efficient use of FPGA primitives (e.g. DSP blocks) in high performance applications, control flow strategies and automating the testing of designs. With specific applications (e.g., audio filtering), the students will also gain an understanding of finite precision effects, trade-offs in design (resource/performance with memory for instance) and get an exposure to designing system on chip applications with high-level synthesis flows. The module descriptor can be found here. The module also offers an outlook to research & developent in the area of reconfigurable architectures and applications with guest speakers from the industry.Hilary Term (Jan--Apr)
EEU3C7: Digital Systems Design
Digital systems design is an introductory module in VHSIC hardware design using Verilog. The module is taken by the 3rd year cohort in the electronics/electronics & computer/computer engineering stream (C/CD/D) students in the School of Engineering. The module introduces Verilog constructs to design simple combinatorial circuits and sequential logic, building on these to design data processing paths and control flow logic (state machines) in the lab using Field Programmable Gate Arrays (FPGAs) as the target hardware platform. The module also delves into non-synthesizable constructs for building test benches to debug digital designs prior to synthesis and circuit generation from high-level Verilog descriptions. The module descriptor can be found here
EEU4C21/CSP55031: Open Reconfigurable Networks
Open Reconfigurable Networks introduces the concept of reconfigurable software defined networks tackling both wired and wireless networking paradigms. The module delves into data and control plane seperation in wired and wireless systems and how both paradigms benefit from them through SDN and SDR. The wireless part specifically goes into the implementation of SDR systems and its applications in shared spectrum-based communication systems and opportunistic spectrum access. The module is laboratory-led with students building SDR systems using ADALM Pluto devices and MATLAB/Simulink backends. The wired section is led by Prof. M. Ruffini from the School of Computer Science and Statistics. The module descriptor can be found here